| Offered Semester | SoSe-2026 |
|---|---|
| Lecturer(s) | Prof. Dr. Estela Suarez Dr. Nam Ho |
| Module (BASIS) | BASIS_MA-INF-1225 |
| eCampus | TBD: eCampus_MA-INF-1225 |
| Type of Lecture | LAB |
| Credits | 9 CP |
| Research Area | High Performance Computing |
| Language | English |
| Group size | 2 students per group |
| Max. Number Participants | 8 (4 groups of 2) |
| Date | When | Where |
|---|---|---|
| Deadline Registration | 15.03.2026 | Email to both lecturers |
| Introductory Workshop | 15.04.2026 10:00-12:00 16.04.2026 10:00-12:00 21.04.2026 10:00-12:00 23.04.2026 10:00-12:00 28.04.2026 10:00-12:00 | Seminar-Room 0.016 |
| 1 day per Group (6h) Tutored Lab | JSC, Jülich | dates TBD bilaterally (04-15.05.2026) |
| 4-6 weeks Project Work | Btw. 15.05.2026-26.06.2026 | Home Work |
| Bi-weekly Tutor meeting | Every 2nd Friday 22.05.2026 10:00-12:00 05.06.2026 10:00-12:00 19.06.2026 10:00-12:00 26.06.2026 10:00-12:00 | Seminar-Room 0.016 |
| Deadline Report | 05.07.2026 | GitLab submission |
| Final presentation | 10.07.2026 | Seminar-Room 0.016 |
Processor Co-design content: Revise the fundamentals of computer architecture, explore co-design methodology using simulators to optimize memory subsystems, instruction-level parallelism, vector extension units, acceleration techniques for specific computational tasks.
Technical skills:
Soft skills: Ability to properly present the performed work and results obtained and to classify the own results into the state-of-the-art. Prepare readable documentation of software.
| # | Topics | Content | Project Goal |
|---|---|---|---|
| A | Memory System Exploration | Cache hierarchies, memory technologies, memory prefetching | Evaluating prefetchers, cache structures, HBM vs DDR |
| B | Instruction Level Parallelism (ILP) | Dynamic/static scheduling, multiple issue, branch prediction | Exploring in-order vs out-of-order, branch predictor, Inflight-memory request buffers |
| C | Data Level Parallelism (DLP) | Vector extensions. Vector length agnostic (e.g. Arm SVE, RISCVV) vs fix-vector length (e.g. Intel AVX) | Exploring vector lengths |
| D | Thread-level parallelism (TLP) | Directory-based vs Snooping coherence | Evaluating coherence protocols with a NoC 2D-Mesh |
A report and an oral presentation of the results will be the main grading elements.